A Reconfigurable Applcation Specific Instruction Set Processor for Viterbi and Log-MAP Decoding

Author:

Vogt Timo,Wehn Norbert

Publisher

IEEE

Cited by 16 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. ASIP for 5G and Beyond: Opportunities and Vision;IEEE Transactions on Circuits and Systems II: Express Briefs;2021-03

2. Parallel ASIP Based Design of Turbo Decoder;Lecture Notes in Electrical Engineering;2014-11-02

3. Integrated video motion estimator with Retinex-like pre-processing for robust motion analysis in automotive scenarios: algorithmic and real-time architecture design;Journal of Real-Time Image Processing;2010-02-10

4. An ASIP encoder for Quasi-Cyclic LDPC codes;2009 IEEE International Conference on Intelligent Computing and Intelligent Systems;2009-11

5. An multi-rate LDPC decoder based on ASIP for DMB-TH;2009 IEEE 8th International Conference on ASIC;2009-10

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