Design and verification of RISC-V CPU based on HLS and UVM
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx7/9574103/9574447/09574575.pdf?arnumber=9574575
Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Five Stage Pipelined MIPS Processor Verification Scoreboard Module using UVM;2023 International Conference in Advances in Power, Signal, and Information Technology (APSIT);2023-06-09
2. Embedded Processor Design in FPGA by ASMD-FSMD and FSM-Single Techniques;Computer Information Systems and Industrial Management;2022
3. Reducing Development Time of Embedded Processors by Using FSM-Single and ASMD-FSMD Techniques;New Advances in Dependability of Networks and Systems;2022
4. A rigorous approach to microprocessor verification using UVM;i-manager’s Journal on Electronics Engineering;2022
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