A unified FinFET reliability model including high K gate stack dynamic threshold voltage, hot carrier injection, and negative bias temperature instability-Reference-Cited by-同舟云学术

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A unified FinFET reliability model including high K gate stack dynamic threshold voltage, hot carrier injection, and negative bias temperature instability

Published:2009-03 Issue: Volume: Page:
ISSN:
Container-title:2009 10th International Symposium on Quality of Electronic Design
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Author:

Chenyue Ma ,Bo Li ,Lining Zhang ,Jin He ,Xing Zhang ,Xinnan Lin ,Mansun Chan

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/4804412/4810250/04810262.pdf?arnumber=4810262

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Reliable and high performance asymmetric FinFET SRAM cell using back-gate control;Microelectronics Reliability;2020-01

2. Impact of Negative Bias Temperature Instability on Gate-All-Around Flip-Flops;Journal of Electronic Testing;2019-02

3. An Aging-Aware Reliable FinFET-Based Low-Power 32-Word $$\times $$ × 32-bit Register File;Circuits, Systems, and Signal Processing;2017-09-01

4. Compact NBTI Reliability Modeling in Si Nanowire MOSFETs and Effect in Circuits;IEEE Transactions on Device and Materials Reliability;2017-06

5. A Near-Threshold Soft Error Resilient 7T SRAM Cell with Low Read Time for 20 nm FinFET Technology;Journal of Electronic Testing;2017-05-22

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