Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes

Author:

Fonseca R. Alves,Dilillo L.,Bosio A.,Girard P.,Pravossoudovitch S.,Virazel A.,Badereddine N.

Publisher

IEEE

Cited by 11 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Learning-Based Characterization Models for Quality Assurance of Emerging Memory Technologies;2023 IEEE European Test Symposium (ETS);2023-05-22

2. On Using Cell-Aware Methodology for SRAM Bit Cell Testing;2023 IEEE European Test Symposium (ETS);2023-05-22

3. Hard-to-Detect Fault Analysis in FinFET SRAMs;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2021-06

4. On-Chip Area and Test Time Effective Weak Resistive Open Defect Detection Technique for Cache Memory;2021 IEEE 12th Latin America Symposium on Circuits and System (LASCAS);2021-02-21

5. Comparing the Impact of Power Supply Voltage on CMOS- and FinFET-Based SRAMs in the Presence of Resistive Defects;Journal of Electronic Testing;2020-04

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