Author:
Copetti T.,Balen T. R.,Brum E.,Aquistapace C.,Bolzani Poehls L.
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering
Reference36 articles.
1. Adams RD, Cooley ES (1996) Analysis of a deceptive destructive read memory fault model and recommended testing. In Proc. IEEE North Atlantic Test Workshop
2. Bhattacharya D, Jha NK (2014) FinFETs: from devices to architectures. Adv Electron 2014:1–21
3. Bhoj AN, Simsir MO, Jha NK (2012) Fault models for logic circuits in the multigate era. IEEE Trans Nanotechnol 11(1):182–193
4. Borri S, Hage-Hassan M, Dilillo L, Girard P, Pravossoudovitch S, Virazel A (2005) Analysis of dynamic faults in embedded-SRAMs: implications for memory test. J Electron Test 21(2):169–179
5. Bosio A, Dilillo L, Girard P, Pravossoudovitch S, Virazel A (2012) Advanced test methods for SRAMs. In Proc. 2012 IEEE 30th VLSI Test Symposium (VTS), 300–301
Cited by
3 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献