Early Soft Error Reliability Analysis on RISC-V

Author:

Lodea Nicolas1ORCID,Nunes Willian1ORCID,Zanini Vitor1ORCID,Sartori Marcos1ORCID,Ost Luciano2ORCID,Calazans Ney1ORCID,Garibotti Rafael1ORCID,Marcon Cesar1ORCID

Affiliation:

1. PUCRS University

2. Loughborough University

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,General Computer Science

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Non-intrusive study on FPGA of the SEU sensitivity on the COTS RISC-V VeeR EH1 soft processor from Western Digital;Microprocessors and Microsystems;2024-03

2. Multicore soft error reliability assessment and evaluation of Compiler optimization flag Effects on ARMv7 and ARMv8;2023 IEEE 20th India Council International Conference (INDICON);2023-12-14

3. Improving Reliability of Embedded RISC-V SoC for Low-cost Space Applications;2023 International Conference on Networking and Communications (ICNWC);2023-04-05

4. RISC-V-Based Platforms for HPC: Analyzing Non-functional Properties for Future HPC and Big-Data Clusters;Lecture Notes in Computer Science;2023

5. Soft Error Assessment of CNN Inference Models Running on a RISC-V Processor;2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS);2022-10-24

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