A Multi-stage Fault-Tolerant Multiplier with Triple Module Redundancy (TMR) Technique
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/6497700/6498213/06498349.pdf?arnumber=6498349
Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Calculation Methods and Comparative Analysis of Losses of Active and Electric Energy in Low Voltage Devices;2019 International Ural Conference on Electrical Power Engineering (UralCon);2019-10
2. Design of Fault Tolerant Adders: A Review;Arabian Journal for Science and Engineering;2018-09-25
3. Transient Fault Detection and Recovery Mechanisms in μC/OS-II;Software Analysis, Testing, and Evolution;2018
4. Real-Time FPGA-Based Fault Tolerant and Recoverable Technique for Arithmetic Design Using Functional Triple Modular Redundancy (FRTMR);Proceedings of the Second International Conference on Computational Intelligence and Informatics;2018
5. FPGA Based Multiple Fault Tolerant and Recoverable Technique Using Triple Modular Redundancy (FRTMR);Procedia Computer Science;2016
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