ATPG for Dynamic Burn-In Test in Full-Scan Circuits
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/4030717/4030718/04030744.pdf?arnumber=4030744
Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. About the Correlation between Logical Identified Faulty Gates and their Layout Characteristics;2023 IEEE 29th International Symposium on On-Line Testing and Robust System Design (IOLTS);2023-07-03
2. A Low-Cost Burn-In Tester Architecture to Supply Effective Electrical Stress;IEEE Transactions on Computers;2023-05-01
3. A Toolchain to Quantify Burn-In Stress Effectiveness on Large Automotive System-on-Chips;IEEE Access;2023
4. A novel Pattern Selection Algorithm to reduce the Test Cost of large Automotive Systems-on-Chip;2022 IEEE 23rd Latin American Test Symposium (LATS);2022-09-05
5. An innovative Strategy to Quickly Grade Functional Test Programs;2022 IEEE International Test Conference (ITC);2022-09
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