A 4-bit 4.5-ns-Latency Pseudo-ReRAM Computing-In-Memory Macro With Self Error-Correcting DTC-Based WL Drivers and 6-bit CDAC-Less Column ADCs Having Ultra-Narrow Pitch-Reference-Cited by-同舟云学术

A 4-bit 4.5-ns-Latency Pseudo-ReRAM Computing-In-Memory Macro With Self Error-Correcting DTC-Based WL Drivers and 6-bit CDAC-Less Column ADCs Having Ultra-Narrow Pitch

Published:2023-09 Issue:9 Volume:70 Page:3228-3232
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Kim Jongho¹^ORCID,Oh Young H.²^ORCID,Kim Hyeonsik¹^ORCID,Lee Jae W.³^ORCID,Kim Jintae¹^ORCID

Affiliation:

1. Department of Electrical and Electronics Engineering, Konkuk University, Seoul, South Korea

2. Samsung Advanced Institute of Technology, Suwon, South Korea

3. Department of Computer Science and Engineering, Seoul National University, Seoul, South Korea

Funder

Samsung Chip Interconnect Solutions Research Funding

Ministry of Science and ICT, South Korea

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8920/10235305/10151931.pdf?arnumber=10151931

Reference15 articles.

1. ARCHON: A 332.7TOPS/W 5b Variation-Tolerant Analog CNN Processor Featuring Analog Neuronal Computation Unit and Analog Memory

2. 16.1 A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91 to 195.7TOPS/W for Tiny AI Edge Devices

3. Enabling Lower-Power Charge-Domain Nonvolatile In-Memory Computing With Ferroelectric FETs

4. Efficient and Robust Nonvolatile Computing-In-Memory Based on Voltage Division in 2T2R RRAM With Input-Dependent Sensing Control

5. 15.4 A 22nm 2Mb ReRAM Compute-in-Memory Macro with 121-28TOPS/W for Multibit MAC Computing for Tiny AI Edge Devices