A 1.5 V 2 GS/s 82.1 dB-SFDR Track and Hold Circuit Based on the Time-Divided Post-Distortion Cancelation Technique
Author:
Affiliation:
1. School of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea
Funder
Institute of Information & Communications Technology Planning & Evaluation (IITP) Grant
Korea Government
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8920/9969381/09877933.pdf?arnumber=9877933
Reference10 articles.
1. A 12-b 18-GS/s RF Sampling ADC With an Integrated Wideband Track-and-Hold Amplifier and Background Calibration
2. A 13Bit 5GS/S ADC with Time-Interleaved Chopping Calibration in 16NM FinFET
3. Fully bipolar, 120-Msample/s 10-b track-and-hold circuit
4. A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology
5. A 14 Bit 1 GS/s RF Sampling Pipelined ADC With Background Calibration
Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. An Active Track and Hold Circuit With Linearity Enhancement Technique and Its Analysis Using Volterra Series;IEEE Access;2024
2. A 1.5V 500MHz Fully Differential CMOS Sample and Hold Circuit Using Double Sampling;2023 9th International Conference on Computer and Communications (ICCC);2023-12-08
3. A Skew-Insensitive Switched Source-Follower Analog Frontend for Time-Interleaved ADCs;2023 18th Conference on Ph.D Research in Microelectronics and Electronics (PRIME);2023-06-18
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