A Two-Phase Multi-Bit Incremental ADC With Variable Loop Order-Reference-Cited by-同舟云学术

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A Two-Phase Multi-Bit Incremental ADC With Variable Loop Order

Published:2023-08 Issue:8 Volume:70 Page:2724-2728
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Chen Kaiquan¹^ORCID,Wang Biao²^ORCID,Liu Yan¹^ORCID,Ye Fan³^ORCID,Sin Sai-Weng⁴,Wang Guoxing¹^ORCID,Lian Yong⁵^ORCID,Qi Liang¹^ORCID

Affiliation:

1. Department of Micro–Nano Electronics, Shanghai Jiao Tong University, Shanghai, China

2. Shanghai X-Ring Technology Company Ltd., Shanghai, China

3. State Key Laboratory of ASIC and Systems, Fudan University, Shanghai, China

4. State Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, University of Macau, Macau, China

5. Department of EECS, York University, Toronto, Canada

Funder

National Key Research and Development Program of China

Shanghai Pujiang Program

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8920/10198497/10061593.pdf?arnumber=10061593

Reference19 articles.

1. A 0.9-V DAC-Calibration-Free Continuous-Time Incremental Delta–Sigma Modulator Achieving 97-dB SFDR at 2 MS/s in 28-nm CMOS

2. High-order multi-bit incremental converter with smart-DEM algorithm;liu;Proc IEEE Int Symp Circuits Syst (ISCAS),2013

3. A Dynamic Power Reduction Technique for Incremental $\Delta\Sigma$ Modulators

4. A high resolution multi-bit incremental converter insensitive to DAC mismatch error;wang;Proc Ph D Rese Microelectron Electron Conf (PRIME),2016

5. A 1.2V 86dB SNDR 500kHz BW Linear-Exponential Multi-Bit Incremental ADC Using Positive Feedback in 65nm CMOS

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