A Digital Background Calibration Circuit for Coarse-Fine Timing Mismatch in VCO-Based ADCs-Reference-Cited by-同舟云学术

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A Digital Background Calibration Circuit for Coarse-Fine Timing Mismatch in VCO-Based ADCs

Published:2024-08 Issue:8 Volume:71 Page:3650-3654
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Smith Shea¹^ORCID,Tajalli Armin²^ORCID,Kuan Yen-Cheng³^ORCID,Chiang Shiuh-Hua Wood¹^ORCID

Affiliation:

1. Electrical and Computer Engineering Department, Brigham Young University, Provo, UT, USA

2. Electrical and Computer Engineering Department, University of Utah, Salt Lake City, UT, USA

3. International College of Semiconductor Technology, National Yang Ming Chiao Tung University, Hsinchu, Taiwan

Funder

National Aeronautics and Space Administration

National Science and Technology Council, Taiwan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/8920/10617442/10443877.pdf?arnumber=10443877

Reference14 articles.

1. Two-stage ΔΣ ADC with noise-coupled VCO-based quantizer

2. An Adaptive-Resolution Quasi-Level-Crossing Delta Modulator With VCO-Based Residue Quantizer

3. A 50 MHz bandwidth 54.2 dB SNDR reference-free stochastic ADC using VCO-based quantizers

4. A 100-MS/s–5-GS/s, 13–5-bit Nyquist-Rate Reconfigurable Time-Domain ADC

5. A hybrid SAR-VCO ΔΣ ADC with first-order noise shaping

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