Methodologies for Evaluating and Measuring Capacitance Mismatch in CMOS Integrated Circuits-Reference-Cited by-同舟云学术

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Methodologies for Evaluating and Measuring Capacitance Mismatch in CMOS Integrated Circuits

Published:2017-02 Issue:2 Volume:64 Page:101-105
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Soares Carlos F. T.,Petraglia A.,de Campos Gustavo S.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8920/7835744/07453165.pdf?arnumber=7453165

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3. CMOS Switched-Capacitor DSB-SSB Converter Using a Hilbert Transformer;IEEE Transactions on Circuits and Systems II: Express Briefs;2018-11

4. Performance of analogue, digital and hybrid finite impulse response filter banks affected by realisation errors and noise;IET Signal Processing;2018-10

5. Pseudo-parallel sigma-delta modulator for electrical energy measurement applications;Analog Integrated Circuits and Signal Processing;2017-12-02

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