A Low-Power 4-PAM Transceiver Using a Dual-Sampling Technique for Heterogeneous Latency-Sensitive Network-on-Chip
Author:
Funder
NSF Grants
NSF CAREER
SRC
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8920/7115238/07001190.pdf?arnumber=7001190
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2. A Novel Multifunctional Negative Group Delay Circuit for Realizing Band-Pass, High-Pass and Low-Pass;Electronics;2021-07-20
3. A 32 Gb/s PAM-16 TX and ADC-Based RX AFE with 2-tap embedded analog FFE in 28 nm FDSOI;Microelectronics Journal;2021-02
4. A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS;IEEE Transactions on Circuits and Systems I: Regular Papers;2021-01
5. Hybrid bidirectional transceiver for multipoint‐to‐multipoint signalling across on‐chip global interconnects;IET Circuits, Devices & Systems;2020-09
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