Hybrid bidirectional transceiver for multipoint‐to‐multipoint signalling across on‐chip global interconnects
Author:
Affiliation:
1. Department of E&ECEUniversity of TorontoCanada
2. Department of E&ECEIndian Institute of TechnologyKharagpurIndia
Funder
Indian Institute of Technology Kharagpur
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering,Control and Systems Engineering
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cds.2019.0465
Reference27 articles.
1. Bashirullah R. Liu W. Cavin R.et al.: ‘A 16 Gb/s adaptive bandwidth on‐chip bus based on hybrid current/voltage mode signaling’.2004 Symp. on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No. 04CH37525) Honolulu HI USA 2004 pp.392–393
2. Chen M. Chang M.F. Yang C.K.: ‘A low‐PDP and low‐area repeater using passive CTLE for on‐chip interconnects’.2015 Symp. on VLSI Circuits (VLSI Circuits) Kyoto Japan 2015 pp.C244–C245
3. An energy‐efficient equalized transceiver for RC‐dominant channels;Kim B.;IEEE J. Solid‐State Circuits,2010
4. Current-Mode Full-Duplex Transceiver for Lossy On-Chip Global Interconnects
5. Lee S.K. Lee S.H. Sylvester D.et al.: ‘A 95 fJ/b current‐mode transceiver for 10 mm on‐chip interconnect’.2013 IEEE Int. Solid‐State Circuits Conf. Digest of Technical Papers (ISSCC) San Francisco CA USA 2013 pp.262–263
Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Use of current-mode and voltage-mode receivers together for on-chip multipoint-to-multipoint data transmission across global interconnects;2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID);2024-01-06
2. A 32 Gb/s, 0.42 pJ/bit Passive Hybrid Simultaneous Bidirectional Transceiver for Die-to-Die Links;2023 IEEE International Symposium on Circuits and Systems (ISCAS);2023-05-21
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