Current-Mode Full-Duplex Transceiver for Lossy On-Chip Global Interconnects

Author:

Wary NijwmORCID,Mandal Pradip

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 23 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A 0.2 pJ/bit, Energy-Efficient, Half-Rate Hybrid Circuit Topology at 6-Gb/s in 1.2V, 65 nm CMOS;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

2. A 0.186 pJ/bit, 6-Gb/s, Energy-Efficient, Half-Rate Hybrid Circuit Topology in 1.2V, 65 nm CMOS;2024 25th International Symposium on Quality Electronic Design (ISQED);2024-04-03

3. Use of current-mode and voltage-mode receivers together for on-chip multipoint-to-multipoint data transmission across global interconnects;2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID);2024-01-06

4. Energy Efficient Resistor-Transconductor Hybrid-Based Full-Duplex Transceiver for Serial Link;IEEE Transactions on Circuits and Systems I: Regular Papers;2024

5. A Linear Ratioed Impedance and Driver-Based True Full-Duplex IO with Background Self-Interference Cancellation;2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS);2023-08-06

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