A Two-Cycle Lock-In Time ADPLL Design Based on a Frequency Estimation Algorithm
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx5/8920/5484963/05471177.pdf?arnumber=5471177
Cited by 28 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Fast Settling Phase-Locked Loops: A Comprehensive Survey of Applications and Techniques [Feature];IEEE Circuits and Systems Magazine;2024
2. A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time;IEEE Journal of Solid-State Circuits;2022-12
3. A Fast-Locking All-Digital PLL With Triple-Stage Phase-Shifting;IEEE Access;2021
4. A wide range high resolution digital controlled oscillator with high precision time to digital convertor for optimal sampling digital PLL;Microprocessors and Microsystems;2020-04
5. DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW;Jurnal Teknologi;2019-12-04
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