Universal Stability Criterion for Type-I Sampling Phase-Locked Loops

Author:

Huang Yunbo1ORCID,Chen Yong1ORCID,Mak Pui-In1ORCID,Martins Rui P.1ORCID

Affiliation:

1. State-Key Laboratory of Analog and Mixed-Signal VLSI and IME/ECE-FST, University of Macau, Macau, China

Funder

Science and Technology Development Fund, Macau, SAR

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Reference17 articles.

1. A Closed-Form Transfer Function for Sample and Hold Master Slave Sampling Filter

2. A 25.4-to-29.5GHz 10.2mW isolated sub-sampling PLL achieving ?252.9dB jitter-power FoM and ?63dBc reference spur;yang;IEEE Int Solid-State Circuits Conf Dig Tech Papers,2019

3. Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector

4. A 2.4 GHz 4 mW Integer-N Inductorless RF Synthesizer

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