A High-Logic-Density, Low-Power Control Character Detection and Identification Circuit for the JESD204B Data Link Layer-Reference-Cited by-同舟云学术

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A High-Logic-Density, Low-Power Control Character Detection and Identification Circuit for the JESD204B Data Link Layer

Published:2023-04 Issue:4 Volume:70 Page:1600-1604
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Wang Qiushi¹^ORCID,Yin Peng²^ORCID,Wu Nairiga¹,Bermak Amine³^ORCID,Tang Fang¹^ORCID

Affiliation:

1. School of Microelectronics and Communication Engineering, Chongqing University, Chongqing, China

2. School of Physics and Electronics, Henan University, Kaifeng, China

3. College of Science and Engineering, Hamad Bin Khalifa University, Doha, Qatar

Funder

Natural Science Foundation of Chongqing, China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8920/10083009/09969940.pdf?arnumber=9969940

Reference14 articles.

1. BLASTP-ACC: Parallel Architecture and Hardware Accelerator Design for BLAST-Based Protein Sequence Alignment

2. A Highly Parameterized and Efficient FPGA-Based Skeleton for Pairwise Biological Sequence Alignment

3. Adaptive Dynamic Programming for Control: A Survey and Recent Advances

4. A general method applicable to the search for similarities in the amino acid sequence of two proteins

5. Feature Selection via Global Redundancy Minimization

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. High Logic Density Cyclic Redundancy Check and Forward Error Correction Logic Sharing Encoding Circuit for JESD204C Controller;IEEE Transactions on Circuits and Systems I: Regular Papers;2024

2. Design and Implementation of High-Speed Serial Transmission for ADC Based on JESD204B;2023 IEEE 3rd International Conference on Intelligent Technology and Embedded Systems (ICITES);2023-10-27

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