Transition Detector-Based Radiation-Hardened Latch for Both Single- and Multiple-Node Upsets
Author:
Funder
Waseda University and Toshiba Memory Corporation
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8920/9103104/08755273.pdf?arnumber=8755273
Cited by 17 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Novel Radiation Hardened Pre-Discharge Sense Amplifier for Double Data Rate Magnetic Random Access Memory;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-07
2. A High-Performance Quadruple-Node-Upset-Tolerant Latch Design and an Algorithm for Tolerance Verification of Hardened Latches;Journal of Electronic Testing;2024-02
3. Hardened latch designs based on the characteristic of transistor for mitigating multiple-node-upsets in harsh radiation environments;Microelectronics Journal;2024-01
4. Double-Node-Upset Self-Recoverable Latch Design for Wide Voltage Range Application;IEEE Transactions on Circuits and Systems II: Express Briefs;2024
5. Novel Radiation Hardened DSOT-MRAM Read Peripheral Circuit With Reduced Sensitive Nodes;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-11
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