A 14-Bit 500-MS/s Time-Interleaved ADC With Autocorrelation-Based Time Skew Calibration
Author:
Funder
Tsinghua University
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8920/8653436/08392716.pdf?arnumber=8392716
Cited by 18 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A Novel Calibration Algorithm for ADCs Based on Inverse Mapping by Neural Network;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-07
2. A comprehensive review of time skew background calibration and mitigation techniques in high‐speed time‐interleaved analog‐to‐digital converters;International Journal of Circuit Theory and Applications;2024-06-12
3. A Single-Stage Gain-Boosted Cascode Amplifier With Three-Layer Cascode Feedback Amplifier for Front-End SHA in High-Linearity Pipelined ADC;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024
4. An 18‐bit 1‐GS/s time interleaved analog‐to‐digital converter with timing skew calibration based on an adaptive genetic algorithm;International Journal of Circuit Theory and Applications;2023-06-11
5. A Foreground Mismatch and Memory Harmonic Distortion Calibration Algorithm for TIADC;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-03
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