Hardware/Software Co-Design of Cryptographic SoC Based on RISC-V Virtual Prototype
Author:
Affiliation:
1. School of Integrated Circuits, Guangdong University of Technology, Guangzhou, China
Funder
Basic and Applied Basic Research Foundation of Guangdong Province
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8920/10235305/10102649.pdf?arnumber=10102649
Reference20 articles.
1. Extensible and Configurable RISC-V Based Virtual Prototype
2. Fast Virtual Prototyping for Embedded Computing Systems Design and Exploration
3. gem5-SALAM: A System Architecture for LLVM-based Accelerator Modeling
4. A QEMU and SystemC-Based Cycle-Accurate ISS for Performance Estimation on SoC Development
5. An Efficient and Low-Power Design of the SM3 Hash Algorithm for IoT
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1. Anlu NP: The Abstract Level Modeling of Network Processor for Agile Hardware Design;2024 5th International Conference on Computer Engineering and Application (ICCEA);2024-04-12
2. Design of an SoC Based on 32-Bit RISC-V Processor with Low-Latency Lightweight Cryptographic Cores in FPGA;Future Internet;2023-05-19
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