A 47 TOPS/W 10T SRAM-Based Multi-Bit Signed CIM With Self-Adaptive Bias Voltage Generator for Edge Computing Applications
Author:
Affiliation:
1. Institute of Microelectronics, Agency for Science, Technology and Research (A*STAR), Connexis, Singapore
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8920/10235305/10121807.pdf?arnumber=10121807
Reference18 articles.
1. A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors
2. A 0.506-pJ 16-kb 8T SRAM With Vertical Read Wordlines and Selective Dual Split Power Lines
3. ±CIM SRAM for Signed In-Memory Broad-Purpose Computing From DSP to Neural Processing
4. An SRAM-Based Hybrid Computation-in-Memory Macro Using Current-Reused Differential CCO
5. A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits
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1. SRAM-Based Hybrid Analog Compute-In-memory Architecture to Enhance the Signal Margin;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
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