A 0.6-V 800-MHz All-Digital Phase-Locked Loop With a Digital Supply Regulator-Reference-Cited by-同舟云学术

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A 0.6-V 800-MHz All-Digital Phase-Locked Loop With a Digital Supply Regulator

Published:2012-12 Issue:12 Volume:59 Page:888-892
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Cheng Kuo-Hsing,Liu Jen-Chieh,Huang Hong-Yi

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/8920/6424017/06407963.pdf?arnumber=6407963

Cited by 15 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A comprehensive review: ultra-low power all-digital phase-locked loop RF transceivers for biomedical monitoring applications;Analog Integrated Circuits and Signal Processing;2024-05-13

2. Design of Synthesizable Digital Phase Locked Loops;IPSJ Transactions on System and LSI Design Methodology;2024

3. A 0.25–0.4-V, Sub-0.11-mW/GHz, 0.15–1.6-GHz PLL Using an Offset Dual-Path Architecture With Dynamic Charge Pumps;IEEE Journal of Solid-State Circuits;2021-06

4. A Fractional-N Digitally Intensive PLL Achieving 428-fs Jitter and <-54-dBc Spurs Under 50-mV $_{pp}$ Supply Ripple;IEEE Journal of Solid-State Circuits;2021

5. A Low Supply Voltage All-Digital Phase-Locked Loop With a Bootstrapped and Forward Interpolation Digitally Controlled Oscillator;IEEE Access;2021

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