Background Timing Mismatch Calibration Techniques in High-Speed Time-Interleaved ADCs: A Tutorial Review-Reference-Cited by-同舟云学术

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Background Timing Mismatch Calibration Techniques in High-Speed Time-Interleaved ADCs: A Tutorial Review

Published:2022-06 Issue:6 Volume:69 Page:2564-2569
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Guo Mingqiang¹^ORCID,Sin Sai-Weng¹^ORCID,Qi Liang²^ORCID,Xu Dengke³,Wang Guoxing²^ORCID,Martins Rui P.¹^ORCID

Affiliation:

1. State Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, and the FST-ECE, University of Macau, Macau, China

2. Department of Micro/Nano Electronics, Shanghai Jiao Tong University, Shanghai, China

3. Amicro Semiconductor Company Ltd, Zhuhai, China

Funder

National Key Research and Development Program of China

The Science and Technology Development Fund, Macao, China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8920/9786589/09738817.pdf?arnumber=9738817

Reference47 articles.

1. A 10-bit 2.6-GS/s Time-Interleaved SAR ADC With a Digital-Mixing Timing-Skew Calibration Technique

2. 27.7 A 10b 2.6GS/s time-interleaved SAR ADC with background timing-skew calibration

3. A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR With Digital Background Timing Mismatch Calibration

4. Generalized Method for Extraction of Offset, Gain, and Timing Skew Errors in Time-Interleaved ADCs

5. A 10b 1.6GS/s 12.2mW 7/8-way Split Time-interleaved SAR ADC with Digital Background Mismatch Calibration

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Wideband Timing Mismatch Calibration Design for Time-Interleaved Analog-to-Digital Converters with Fast Convergence;Electronics;2024-06-24

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