A Wideband Timing Mismatch Calibration Design for Time-Interleaved Analog-to-Digital Converters with Fast Convergence
Author:
Affiliation:
1. School of Aeronautics and Astronautics, Zhejiang University, Hangzhou 310027, China
2. China United Network Communications Co., Ltd., Jiangsu Branch, Nanjing 210019, China
Abstract
Publisher
MDPI AG
Link
https://www.mdpi.com/2079-9292/13/13/2459/pdf
Reference29 articles.
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3. A 480 mW 2.6 GS/s 10b Time-Interleaved ADC With 48.5 dB SNDR up to Nyquist in 65 nm CMOS;Doris;IEEE J. Solid-State Circuits,2011
4. Background Timing Mismatch Calibration Techniques in High-Speed Time-Interleaved ADCs: A Tutorial Review;Guo;IEEE Trans. Circuits Syst. II Express Briefs,2022
5. Design Considerations for Interleaved ADCs;Razavi;IEEE J. Solid-State Circuits,2013
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