A Spike-Event-Based Neuromorphic Processor with Enhanced On-Chip STDP Learning in 28nm CMOS
Author:
Funder
Research and Development
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9401028/9401051/09401194.pdf?arnumber=9401194
Cited by 11 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Accelerating BPTT-Based SNN Training with Sparsity-Aware and Pipelined Architecture;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
2. MorphBungee: A 65nm 7.2mm2 27μJ/image Digital Edge Neuromorphic Chip with On-Chip 802 Frame/s Multi-Layer Spiking Neural Network Learning;2023 IEEE Asian Solid-State Circuits Conference (A-SSCC);2023-11-05
3. An Efficient Neuromorphic Implementation of Temporal Coding-Based On-Chip STDP Learning;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-11
4. Unsupervised Learning of Spike-Timing-Dependent Plasticity Based on a Neuromorphic Implementation;2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS);2023-06-11
5. Open the box of digital neuromorphic processor: Towards effective algorithm-hardware co-design;2023 IEEE International Symposium on Circuits and Systems (ISCAS);2023-05-21
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