Device Non-Ideality Effects and Architecture-Aware Training in RRAM In-Memory Computing Modules-Reference-Cited by-同舟云学术

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Device Non-Ideality Effects and Architecture-Aware Training in RRAM In-Memory Computing Modules

Published:2021-05 Issue: Volume: Page:
ISSN:
Container-title:2021 IEEE International Symposium on Circuits and Systems (ISCAS)
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Author:

Wang Qiwen,Park Yongmo,Lu Wei D.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9401028/9401051/09401307.pdf?arnumber=9401307

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2. Design Strategies of 40 nm Split-Gate NOR Flash Memory Device for Low-Power Compute-in-Memory Applications;Micromachines;2023-09-07

3. Side-Channel Attack Analysis on In-Memory Computing Architectures;IEEE Transactions on Emerging Topics in Computing;2023

4. Energy-Efficient IRS-Aided NOMA Beamforming for 6G Wireless Communications;IEEE Transactions on Green Communications and Networking;2022-12

5. End-to-end modeling of variability-aware neural networks based on resistive-switching memory arrays;2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC);2022-10-03

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