A 60-fJ/step 11-ENOB VCO-based CTDSM Synthesized from Digital Standard Cell Library
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/8767369/8780115/08780194.pdf?arnumber=8780194
Cited by 11 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. N Parallel paths for non-linearity mitigation in ring oscillator based analog-to-digital conversion;AEU - International Journal of Electronics and Communications;2023-10
2. Standard-Cell-Based Comparators for Ultra-Low Voltage Applications: Analysis and Comparisons;Chips;2023-08-18
3. A 0.0072-mm2 10-bit 100-MS/s Calibration-free SAR ADC Using Digital Place-and-Route Tools in 40-nm CMOS;2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT);2023-04-17
4. An 80.2-to-89.1dB-SNDR 24k-to-200kHz-BW VCO-Based Synthesized ?S ADC with 105dB SFDR in 28-nm CMOS;2023 IEEE Custom Integrated Circuits Conference (CICC);2023-04
5. Continuous-Time Analog Filters for Audio Edge Intelligence: Review on Circuit Designs [Feature];IEEE Circuits and Systems Magazine;2023
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