High linearity PVT tolerant 100MS/s rail-to-rail ADC driver with built-in sampler in 65nm CMOS-Reference-Cited by-同舟云学术

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High linearity PVT tolerant 100MS/s rail-to-rail ADC driver with built-in sampler in 65nm CMOS

Published:2014-09 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the IEEE 2014 Custom Integrated Circuits Conference
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Author:

Palani Rakesh Kumar,Harjani Ramesh

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/6924030/6945974/06946065.pdf?arnumber=6946065

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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4. Blocker and Clock-Jitter Performance in CT ΣΔ ADCs for Consumer Radio Receivers;Wideband Continuous-time ΣΔ ADCs, Automotive Electronics, and Power Management;2016-08-06

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