ADC
Author:
Publisher
Springer International Publishing
Link
http://link.springer.com/content/pdf/10.1007/978-3-319-46628-6_7
Reference19 articles.
1. Rakesh Kumar Palani, Martin Sturm, and Ramesh Harjani. A 1.56 mw 50 MHz 3rd-Order Filter with Current-Mode Active-RC Biquad and 33 dbm IIP3 in 65 nm CMOS. IEEE Asian Solid state Circuit conference, November 2013.
2. Rakesh Kumar Palani and Ramesh Harjani. High Linearity PVT Tolerant 100MS/S Rail-to-Rail ADC Driver with Built-in Sampler in 65 nm CMOS. IEEE Custom Integrated Circuit Conference, September 2014.
3. Ramesh Harjani and Rakesh Kumar Palani. Design of PVT Tolerant Inverter Based Circuits for Low Supply Voltages. IEEE Custom Integrated Circuit Conference, September 2015.
4. Yan Zhu, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, and Franco Maloberti. A 10 bit 100MS/s reference-free SAR ADC in 90 nm CMOS. IEEE Journal of Solid State Circuits, pages 1111–1121, June 2010.
5. Hideo Nakane, Ryuichi Ujiie, Takashi Oshima, Takaya Yamamoto, Keisuke Kimura, Yuichi Okuda, Kosuke Tsuiji, and Tatsuji Matsuura. A fully integrated SAR ADC using digital correction technique for triple-mode mobile transceiver. IEEE Asian Solid State Circuit Conference, pages 73–76, November 2013.
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