The Design of An LDO Regulator [The Analog Mind]
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/4563670/9805474/09805648.pdf?arnumber=9805648
Reference5 articles.
1. A Transient-Enhanced Low-Quiescent Current Low-Dropout Regulator With Buffer Impedance Attenuation
2. Full On-Chip CMOS Low-Dropout Voltage Regulator
3. The Low Dropout Regulator [A Circuit for All Seasons]
4. Low-dropout on-chip voltage regulator for low-power circuits
5. Optimized frequency-shaping circuit topologies for LDOs
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1. Analysis of Power-Supply-Rejection Enhancement Techniques for Low-Dropout Regulators;IEEE Access;2024
2. Analysis of Low-Dropout Voltage Regulator designed with Gate-All-Around nanosheet transistors;2023 37th Symposium on Microelectronics Technology and Devices (SBMicro);2023-08-28
3. The Design of An LDO Regulator;ITM Web of Conferences;2023
4. Exploring Ways to Minimize Dropout Voltage for Energy-Efficient Low-Dropout Regulators: Viable approaches that preserve performance;IEEE Solid-State Circuits Magazine;2023
5. The Design of a Millimeter-Wave VCO [The Analog Mind];IEEE Solid-State Circuits Magazine;2022
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