A Process and Data Variations Tolerant Capacitive Coupled 10T1C SRAM for In-Memory Compute (IMC) in Deep Neural Network Accelerators
Author:
Affiliation:
1. Indraprastha Institute of Information Technology Delhi,New Delhi,India
2. STMicroelectronics Greater Noida,New Delhi,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9869844/9869845/09870026.pdf?arnumber=9870026
Reference11 articles.
1. Area-Efficient and Variation-Tolerant In-Memory BNN Computing using 6T SRAM Array
2. ChaCha20-in-Memory for Side-Channel Resistance in IoT Edge-Node Devices
3. Actively Compensated Read Assist Technique for 0.6 V Operation of 16 Mb High Density SRAM in 65nm LSTP
4. XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks
5. Design Of High Density Memory Cell Library For Low Voltage Operation In 65nm LSTP Technology
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1. PIC-RAM: Process-Invariant Capacitive Multiplier Based Analog In Memory Computing in 6T SRAM;2023 Design, Automation & Test in Europe Conference & Exhibition (DATE);2023-04
2. Multi-Bit Compute-In Memory Architecture Using a C-2C Ladder Network;IEEE Transactions on Circuits and Systems II: Express Briefs;2023
3. A Common Mode Insensitive Process Tolerant Sense Amplifier Design for In Memory Compute Applications in 65nm LSTP Technology;2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID);2023-01
4. Word Line Underdrive Technique to Increase Signal Swing and Linearity for In-Memory Compute Applications (IMC) in 65nm LSTP technology;2022 IEEE 19th India Council International Conference (INDICON);2022-11-24
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