Area-Efficient and Variation-Tolerant In-Memory BNN Computing using 6T SRAM Array

Author:

Kim Jinseok,Koo Jongeun,Kim Taesu,Kim Yulhwa,Kim Hyungjun,Yoo Seunghyun,Kim Jae-Joon

Publisher

IEEE

Cited by 71 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A Dual 7T SRAM-Based Zero-Skipping Compute- In-Memory Macro With 1-6b Binary Searching ADCs for Processing Quantized Neural Networks;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-08

2. An XOR-10T SRAM computing-in-memory macro with current MAC operations and time-to-digital conversion for BNN edge processors;AEU - International Journal of Electronics and Communications;2024-07

3. A 9 Transistor SRAM Featuring Array-level XOR Parallelism with Secure Data Toggling Operation;Proceedings of the Great Lakes Symposium on VLSI 2024;2024-06-12

4. PVT-Insensitive Time-Domain-based In-Memory Computation with Improved Linearity for Binary Neural Networks;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

5. Comparative Assessment of Charge Sharing and Charge Coupling Circuits: An Approach for Optimal In-Memory Computing;2024 7th International Conference on Devices, Circuits and Systems (ICDCS);2024-04-23

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