Area Efficient Computing-in-Memory Architecture Using STT/SOT Hybrid Three Level Cell
Author:
Affiliation:
1. Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Roorkee, Uttarakhand, India
2. High-velocity Product Group (HPG), Intel Technolgy India Pvt. Ltd., Bengaluru, India
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Materials Chemistry,Electrical and Electronic Engineering,Computer Science Applications,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/8782713/9680797/09756330.pdf?arnumber=9756330
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