A debugging method for repairing post-silicon bugs of high performance processors in the fields
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx5/5677390/5681421/05681434.pdf?arnumber=5681434
Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Introduction;Built-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design;2023
2. Fault tolerance on-chip: a reliable computing paradigm using self-test, self-diagnosis, and self-repair (3S) approach;Science China Information Sciences;2018-05-24
3. Automatic Correction of Dynamic Power Management Architecture in Modern Processors;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2018-02
4. Bridging Presilicon and Postsilicon Debugging by Instruction-Based Trace Signal Selection in Modern Processors;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2017-07
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