4-Bit Vedic Multiplier with 18nm FinFET Technology-Reference-Cited by-同舟云学术

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4-Bit Vedic Multiplier with 18nm FinFET Technology

Published:2020-07 Issue: Volume: Page:
ISSN:
Container-title:2020 International Conference on Electronics and Sustainable Communication Systems (ICESC)
language:
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Author:

Saritha P.,Vinitha J.,Sravya S.,Vijay Vallabhuni,Mahesh E.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9145513/9155547/09155707.pdf?arnumber=9155707

Cited by 26 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Investigation on the mechanical properties and microstructural analysis of dissimilar friction stir welding of AA5154/AA7150;Journal of Adhesion Science and Technology;2024-06-08

2. Design and Implementation of High-Speed, Low-Power CMOS D Flip-Flop and Counters using Double Gate FinFET Technology;2024 5th International Conference for Emerging Technology (INCET);2024-05-24

3. Analysis of Serial Adder Using FinFET Based GDI Technique;2024 International Conference on Smart Systems for applications in Electrical Sciences (ICSSES);2024-05-03

4. A novel energy efficient 4-bit vedic multiplier using modified GDI approach at 32 nm technology;Heliyon;2024-05

5. Design and Analysis of 4 Bit Multipliers Using Pass Transistor Logic and Gate Diffusion Input Technique Using 18nm FinFET Technology;2024 7th International Conference on Devices, Circuits and Systems (ICDCS);2024-04-23

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