Low-Power Adiabatic/MTJ LIM-Based XNOR/XOR Synapse and Neuron for Binarized Neural Networks
Author:
Affiliation:
1. University of Tennessee Knoxville,Department of Electrical Engineering and Computer Science,Knoxville,TN,USA
Funder
National Science Foundation CAREER
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10231127/10231154/10231249.pdf?arnumber=10231249
Reference17 articles.
1. XNOR-Bitcount Operation Exploiting Computing-In-Memory With STT-MRAMs
2. XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks;sun;2018 Design Automation & Test in Europe Conference & Exhibition (DATE),2018
3. Hybrid MTJ/CNTFET-Based Binary Synapse and Neuron for Process-in-Memory Architecture
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