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A Design of 6.8 mW All Digital Delay Locked Loop With Digitally Controlled Dither Cancellation for TDC in Ranging Sensor

  • Published:2020 Issue: Volume:8 Page:57722-57732
  • ISSN:2169-3536
  • Container-title:IEEE Access
  • language:
  • Short-container-title:IEEE Access

Author:

Rehman Muhammad Riaz Ur,Hejazi Arash,Ali Imran,Lee Jae Jin,Oh Seong Jin,Pu Younggun,Lee Kang-YoonORCID

Funder

Korea Institute for Advancement of Technology

Ministry of Science, ICT and Future Planning

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

General Engineering,General Materials Science,General Computer Science

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A wide-range and fast-locking all-digital DLL with one-cycle dynamic synchronizing for in-cell touched LC display;Analog Integrated Circuits and Signal Processing;2023-11-10

2. A Wide-Range and High-Linearity Timing Generator with 1.25ps-Resolution;2023 8th International Conference on Integrated Circuits and Microsystems (ICICM);2023-10-20

3. A Resolution-Tunable Low Power Time-to-Digital Converter With an Improved ADDLL Based on a Cyclic Pulse Ring Oscillator;IEEE Transactions on Instrumentation and Measurement;2023

4. Impact of neutron induced Single-Event Multiple Transients in ADDLL based frequency multiplier;AEU - International Journal of Electronics and Communications;2022-09

5. Frequency-range enhanced delay locked loop based on varactor-loaded and current-controlled delay elements;AEU - International Journal of Electronics and Communications;2020-12
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