A Low-Power and Area-Efficient Design of a Weighted Pseudorandom Test-Pattern Generator for a Test-Per-Scan Built-in Self-Test Architecture-Reference-Cited by-同舟云学术

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A Low-Power and Area-Efficient Design of a Weighted Pseudorandom Test-Pattern Generator for a Test-Per-Scan Built-in Self-Test Architecture

Published:2021 Issue: Volume:9 Page:29366-29379
ISSN:2169-3536
Container-title:IEEE Access
language:
Short-container-title:IEEE Access

Author:

Shivakumar Vishnupriya^ORCID,Senthilpari Chinnaiyan^ORCID,Yusoff Zubaida

Funder

Multimedia University

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

General Engineering,General Materials Science,General Computer Science

Link

http://xplorestaging.ieee.org/ielx7/6287639/9312710/09353528.pdf?arnumber=9353528

Cited by 13 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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3. Test Power Reduction through Reordering Algorithm Implementation and Advancements in BIST Architecture;IETE Journal of Research;2024-05-20

4. Adaptive Reconfigurable LFSR: Dynamic Tapping and Reseeding for Enhanced Pseudo Random Number Generation;2024 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS);2024-02-24

5. Build Testbenches for Verification in Shift Register ICs using SystemVerilog;International Journal of Electronics and Telecommunications;2023-12-07

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