A 500 kS/s 8-bit charge recycle based 2-bit per step SAR-ADC-Reference-Cited by-同舟云学术

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A 500 kS/s 8-bit charge recycle based 2-bit per step SAR-ADC

Published:2012-11 Issue: Volume: Page:
ISSN:
Container-title:2012 Third International Conference on Emerging Applications of Information Technology
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Author:

Shrivastava Pankaj,Bhat Kalpana G.,Laxminidhi Tonse,Bhat M. S.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/6389599/6407845/06408018.pdf?arnumber=6408018

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. An 8 bit-ENOB Sampling-rate Reconfigurable Asynchronous SAR ADC with Metastability Watchdog Circuit for Activity-driven Multi-Channel CMOS Readout ASICs for Space Applications;AEU - International Journal of Electronics and Communications;2024-01

2. 1^st-Order Error-Feedback Sampling-Rate Reconfigurable Noise-Shaping SAR ADC for Multi-Channel CMOS Front-End ASICs for Space Applications;2023 21st IEEE Interregional NEWCAS Conference (NEWCAS);2023-06-26

3. A compact 4-to-8-bit nonbinary SAR ADC based on 2 bits per cycle DAC architecture;Sādhanā;2019-05-07

4. An 8 bit 1 MS/s SAR ADC with 7.72-ENOB;Journal of Semiconductors;2017-08

5. A Resolution Independent 2-Bits-per-Cycle SAR ADC;2014 Fifth International Symposium on Electronic System Design;2014-12

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