A compact 4-to-8-bit nonbinary SAR ADC based on 2 bits per cycle DAC architecture
Author:
Publisher
Springer Science and Business Media LLC
Subject
Multidisciplinary
Link
http://link.springer.com/content/pdf/10.1007/s12046-019-1121-1.pdf
Reference17 articles.
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3. Verma N and Chandrakasan A 2007 An ultra low energy 12-bit rate-resolution scalable SAR ADC for wireless sensor nodes. IEEE Journal of Solid-State Circuits 42: 1196–1205
4. O’Driscoll S, Shenoy K and Meng T 2011 Adaptive resolution ADC array for an implantable neural sensor. IEEE Transactions on Biomedical Circuits and Systems 5: 120–130
5. Wei H Chan C H Chio U F, Sin S W, U S P, Martins R and Maloberti F 2012 An 8-b 400-MS/s 2-b-per-cycle SAR ADC with resistive DAC. IEEE Journal of Solid-State Circuits 47: 2763–2772
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