Automatic generation of instruction sequences targeting hard-to-detect structural faults in a processor-Reference-Cited by-同舟云学术

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Automatic generation of instruction sequences targeting hard-to-detect structural faults in a processor

Published:2006-10 Issue: Volume: Page:
ISSN:1089-3539
Container-title:2006 IEEE International Test Conference
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Author:

Gurumurthy Sankar,Vasudevan Shobha,Abraham Jacob

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/4079296/4042774/04079354.pdf?arnumber=4079354

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Harpocrates: Breaking the Silence of CPU Faults through Hardware-in-the-Loop Program Generation;2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA);2024-06-29

2. Self-Test Library Generation for In-Field Test of Path Delay Faults;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-11

3. Using Formal Methods to Support the Development of STLs for GPUs;2022 IEEE 31st Asian Test Symposium (ATS);2022-11

4. On Test Generation for Microprocessors for Extended Class of Functional Faults;IFIP Advances in Information and Communication Technology;2020

5. Exploring System Availability During Software-Based Self-Testing of Multi-core CPUs;Journal of Electronic Testing;2018-01-27

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