Anatomy of On-Chip Memory Hardware Fault Effects Across the Layers

Author:

Papadimitriou George1ORCID,Gizopoulos Dimitris1ORCID

Affiliation:

1. National and Kapodistrian University of Athens, Greece

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computer Science Applications,Human-Computer Interaction,Information Systems,Computer Science (miscellaneous)

Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Silent Data Corruptions: Microarchitectural Perspectives;IEEE Transactions on Computers;2023-11

2. Impact of Voltage Scaling on Soft Errors Susceptibility of Multicore Server CPUs;56th Annual IEEE/ACM International Symposium on Microarchitecture;2023-10-28

3. Estimating the Failures and Silent Errors Rates of CPUs Across ISAs and Microarchitectures;2023 IEEE International Test Conference (ITC);2023-10-07

4. In-Memory Computing: The Emerging Computing Topic in the Post-von Neumann Era;Computer;2023-10

5. Silent Data Corruptions: The Stealthy Saboteurs of Digital Integrity;2023 IEEE 29th International Symposium on On-Line Testing and Robust System Design (IOLTS);2023-07-03

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