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A Lightweight Posit Processing Unit for RISC-V Processors in Deep Neural Network Applications

  • Published:2021 Issue: Volume: Page:1-1
  • ISSN:2168-6750
  • Container-title:IEEE Transactions on Emerging Topics in Computing
  • language:
  • Short-container-title:IEEE Trans. Emerg. Topics Comput.

Author:

Cococcioni Marco,Rossi Federico,Ruffaldi Emanuele,Saponara Sergio

Funder

Italian Ministry of Education and Research MIUR

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computer Science Applications,Human-Computer Interaction,Information Systems,Computer Science (miscellaneous)

Cited by 22 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design of a novel low-latency parameterizable posit adder/subtractor using leading one predictor in FPGA;Digital Signal Processing;2024-12

2. Research on High-Efficiency Asynchronous Superscalar Processors: (PhD Forum Paper);2024 IEEE 35th International Conference on Application-specific Systems, Architectures and Processors (ASAP);2024-07-24

3. Implementation of Hardware Trace Buffer Module for RISC-V Processor Core;2024 31st International Conference on Mixed Design of Integrated Circuits and System (MIXDES);2024-06-27

4. Big-PERCIVAL: Exploring the Native Use of 64-Bit Posit Arithmetic in Scientific Computing;IEEE Transactions on Computers;2024-06

5. Efficient Verification Framework for RISC-V Instruction Extensions with FPGA Acceleration;2024 2nd International Symposium of Electronics Design Automation (ISEDA);2024-05-10
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