1. High speed NP-CMOS and multi-output dynamic full adder cells;mirzaee;International Journal of Electrical and Electronics Engineering 4 4,2010
2. A novel low-power full-adder cell with new technique in designing logical gates based on static CMOS inverter
3. Design and simulation of an ultra-low power high performance CMOS logic: DMTGDI;pashaki;INTEGRATION the VLSIjournal,2016
4. A New Technique for Enhancing Performance in Full Adder Circuit;uma;second International Conference on Communication Computing & Security [ICCCS-2012 Procedia Technology,0
5. A New Low Power Dynamic Full Adder Cell Based on Majority Function;foroutan;World Applied Sciences Journal,2008