A Novel Low Power and High Speed 9- Transistors Dynamic Full-Adder Cell Simulation and Design-Reference-Cited by-同舟云学术

A Novel Low Power and High Speed 9- Transistors Dynamic Full-Adder Cell Simulation and Design

Published:2023-07-09 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE Symposium on Computers and Communications (ISCC)
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Author:

Rahimi Parisa¹,Tabany Myasar¹,Pourmoafi Seyedali¹

Affiliation:

1. School of Physics, Engineering, and Computer Science. University of Hertfordshire ALI0 9AB Hatfield,Networks, Security and Systems Research Group,Hertfordshire,UK

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10217219/10217829/10217831.pdf?arnumber=10217831

Reference20 articles.

1. High speed NP-CMOS and multi-output dynamic full adder cells;mirzaee;International Journal of Electrical and Electronics Engineering 4 4,2010

2. A novel low-power full-adder cell with new technique in designing logical gates based on static CMOS inverter

3. Design and simulation of an ultra-low power high performance CMOS logic: DMTGDI;pashaki;INTEGRATION the VLSIjournal,2016

4. A New Technique for Enhancing Performance in Full Adder Circuit;uma;second International Conference on Communication Computing & Security [ICCCS-2012 Procedia Technology,0

5. A New Low Power Dynamic Full Adder Cell Based on Majority Function;foroutan;World Applied Sciences Journal,2008

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