Path delay fault diagnosis in combinational circuits with implicit fault enumeration-Reference-Cited by-同舟云学术

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Path delay fault diagnosis in combinational circuits with implicit fault enumeration

Published:2001 Issue:10 Volume:20 Page:1226-1235
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Pant P.,Yuan-Chieh Hsu ,Gupta S.K.,Chatterjee A.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx5/43/20593/00952739.pdf?arnumber=952739

Cited by 14 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Operations on Multiple Transition Faults without Enumeration;MATEC Web of Conferences;2016

2. Scan-Based Speed-Path Debug for a Microprocessor;IEEE Design & Test of Computers;2012-08

3. Techniques to Prioritize Paths for Diagnosis;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2010-04

4. Diagnosis of path delay faults based on low-coverage tests;IET Computers & Digital Techniques;2010-03-01

5. Test and Diagnostic Trends for Nanometer Technology;IETE Technical Review;2010

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