ASIC Design and Implementation of Ten Gigabit Ethernet Transceiver
Author:
Affiliation:
1. Benha University- Egypt,Benha Faculty of Engineering,Electrical Engineering Department
2. Air Defence Collage,Alexandria,Egypt
3. Air Defense College, Alexandria University,Alexandria,Egypt
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10620403/10620452/10620560.pdf?arnumber=10620560
Reference18 articles.
1. FPGA implementation of 1000base-x Ethernet physical layer core
2. Fibre Optic Communication
3. The Current Ethernet Specifications,2018
4. 8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS
5. Design of a High Speed XAUI Based on Dynamic Reconfigurable Transceiver IP Core
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