FPGA implementation of 1000base-x Ethernet physical layer core
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Published:2018-09-10
Issue:4
Volume:7
Page:2106
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ISSN:2227-524X
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Container-title:International Journal of Engineering & Technology
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language:
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Short-container-title:IJET
Author:
Salem Eman,Zekry Abdelhalim,Labeb Hossam,Tawfik Radwa
Abstract
This paper introduces the field programmable gate array FPGA implementation of 1000BASE-X PHY Physical Layer for gigabit Ethernet over fiber optic cable. The implementation is achieved by developing VHDL model for all its building blocks including the physical coding sub layer, PCS, and the physical medium attachment, PMA. The VHDL code is simulated using XILINX ISE14.7 and synthesized on Xilinx Virtex6 FPGA chip. Measured results show that the designed and implemented Ethernet transceiver works successfully at 1.32 Gb/s, 2.5V supply with reduced power consumption.
Publisher
Science Publishing Corporation
Subject
Hardware and Architecture,General Engineering,General Chemical Engineering,Environmental Engineering,Computer Science (miscellaneous),Biotechnology
Cited by
1 articles.
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