FPGA implementation of 1000base-x Ethernet physical layer core

Author:

Salem Eman,Zekry Abdelhalim,Labeb Hossam,Tawfik Radwa

Abstract

This paper introduces the field programmable gate array FPGA implementation of 1000BASE-X PHY Physical Layer for gigabit Ethernet over fiber optic cable. The implementation is achieved by developing VHDL model for all its building blocks including the physical coding sub layer, PCS, and the physical medium attachment, PMA. The VHDL code is simulated using XILINX ISE14.7 and synthesized on Xilinx Virtex6 FPGA chip. Measured results show that the designed and implemented Ethernet transceiver works successfully at 1.32 Gb/s, 2.5V supply with reduced power consumption.  

Publisher

Science Publishing Corporation

Subject

Hardware and Architecture,General Engineering,General Chemical Engineering,Environmental Engineering,Computer Science (miscellaneous),Biotechnology

Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. ASIC Design and Implementation of Ten Gigabit Ethernet Transceiver;2024 International Telecommunications Conference (ITC-Egypt);2024-07-22

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