A 12.5-Gb/s Parallel Phase Detection Clock and Data Recovery Circuit in 0.13-<tex>$muhbox m$</tex>CMOS-Reference-Cited by-同舟云学术

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A 12.5-Gb/s Parallel Phase Detection Clock and Data Recovery Circuit in 0.13-$muhbox m$CMOS

Published:2006-09 Issue:9 Volume:41 Page:2052-2057
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:en
Short-container-title:IEEE J. Solid-State Circuits

Author:

Ohtomo Y.,Nishimura K.,Nogawa M.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/35458/01683896.pdf?arnumber=1683896

Cited by 10 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 2.41-pJ/bit 5.4-Gb/s Dual-Loop Reference-Less CDR With Fully Digital Quarter-Rate Linear Phase Detector for Embedded DisplayPort;IEEE Transactions on Circuits and Systems I: Regular Papers;2019-08

2. Bang-bang cycle-slip detector improves jitter-tolerance in SONET PLL/DLL CDR;International Journal of Circuit Theory and Applications;2016-02-28

3. A 5.4-Gb/s Clock and Data Recovery Circuit Using Seamless Loop Transition Scheme With Minimal Phase Noise Degradation;IEEE Transactions on Circuits and Systems I: Regular Papers;2012-11

4. A Dual-Loop Clock and Data Recovery Circuit With Compact Quarter-Rate CMOS Linear Phase Detector;IEEE Transactions on Circuits and Systems I: Regular Papers;2012-06

5. Non-idealities in linear CDR phase detectors;International Journal of Circuit Theory and Applications;2011-10-07

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